GS88136T-11.5I Ver la hoja de datos (PDF) - Giga Semiconductor
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GS88136T-11.5I Datasheet PDF : 33 Pages
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Preliminary
GS88118/36T-11/11.5/100/80/66
This SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow
Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are
reported one clock cycle later. (See Write Parity Error Output Timing Diagram.) The Data Parity Mode (DP) pin must be tied
high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data.
Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a
parity error. Multiple Parity Error Output pins may share a common pull-up resistor.
Write Parity Error Output Timing Diagram
CK
DQ
D In A
D In B
D In C
D In D
D In E
tKQ
tHZ
tLZ
tKQX
QE
Err A
Err C
DQ
D In A
D In B
D In C
D In D
D In E
tKQ
tHZ
tLZ
tKQX
QE
Err A
Err C
BPR 1999.05.18
Mode Pin Functions
Mode Name
Burst Order Control
Output Register Control
Power Down Control
ByteSafe Data Parity Control
Pin Name
LBO
FT
ZZ
DP
State
L
H or NC
L
H or NC
L or NC
H
L
H or NC
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, IDD = ISB
Check for Odd Parity
Check for Even Parity
Rev: 1.11 9/2000
7/33
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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