V62C3801024L-100B Ver la hoja de datos (PDF) - Mosel Vitelic Corporation

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V62C3801024L-100B

Ultra Low Power 128K x 8 CMOS SRAM

Mosel Vitelic Corporation  

V62C3801024L(L)

Read Cycle (3,9) (Vcc = 3.0V+0.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)

Parameter

Symbol -55

-70

-85

-100

Unit Note

Read Cycle Time

Min Max Min Max Min Max Min Max

tRC

55 - 70 - 85 - 100 -

ns

Address Access Time

tAA

- 55 - 70 - 85 - 100 ns

Chip Enable Access Time

tACE

- 55 - 70 - 85 - 100 ns

Output Enable Access Time

tOE

- 35 - 40 - 40 -

50

ns

Output Hold from Address Change

tOH

10 - 10 - 10 - 10 -

ns

Chip Enable to Output in Low-Z

tCLZ

10 - 10 - 10 - 10 -

ns

4,5

Chip Disable to Output in High-Z

tCHZ

- 25 - 30 - 35 -

40

ns

4,5

Output Enable to Output in Low-Z

tOLZ

5-5-5-

5

-

ns

4,5

Output Disable to Output in High-Z

tOHZ

- 25 - 25 - 30 -

35

ns

4,5

Power-Up Time

tPU

0-0-0-

0

-

ns

5

Power-Down Time

tPD

- 55 - 70 - 85 - 100 ns

5

Write Cycle (3,11) (Vcc = 3.0V+0.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)

Parameter

Write Cycle Time

Chip Enable to Write End

Address Setup to Write End

Address Setup Time

Write Pulse Width

Write Recovering Time

Data Valid to Write End

Data Hold Time

Write Enable to Output in High-Z

Output Active from Write End

Symbol -55

-70

-85

-100

Unit Note

Min Max Min Max Min Max Min Max

tWC

55 - 70 - 85 - 100 -

ns

tCW

45 - 60 - 70 - 80 -

ns

tAW

45 - 60 - 70 - 80 -

ns

tAS

0-0-0-

0

-

ns

tWP

45 - 50 - 60 - 70 -

ns

tWR

0-0-0-

0

-

ns

tDW

25 - 30 - 35 - 40 -

ns

tDH

0-0-0-

0

-

ns

tWZ

- 25 - 30 - 35 -

40

ns

4,5

tOW

5-5-5-

5

-

ns

4,5

5

REV. 1.1 April 2001 V62C3801024L(L)

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