W6662CF Ver la hoja de datos (PDF) - Winbond

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W6662CF

SCANNER ANALOG FRONT END

Winbond 

Preliminary W6662CF

B. Power down mode

bit [6:0] = don't care.

bit 7 = 1.

The CDSCK1, CDSCK2, ADCCLK and SCLK must hold at stable state after power down mode has

been configured to ensure the W6662 is in low power state. The system must wait at least 10 mS to

ensure that the device is power up completedly if the configuration register is programmed with bit 7

= 0.

PGA Registers

The mapping of PGA registers and PGA_code is:

bit [5:0] PGA_code, bit 5 is MSB, bit 0 is LSB.

bit [7:6] reserved (must set to 0).

The offset registers are described in PGA gain/offset adjustment section.

W6662

SCLK

SEN

SDIO

SMS

chip select

Micro-controller

or

System Controller

or

Core Chip

May drive another peripherals

(a). Three-wired Interface Mode Selected.

W6662

SCLK

SEN

SDI

SDO

DRVDD

chip select

Micro-controller

or

System Controller

or

Core Chip

May drive another peripherals

(b). Four-wired Interface Mode Selected.

Fig. 6-4 Configuration Serial Interface Modes.

Publication Release Date: December 1998

-9-

Revision A1

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