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WT62P1

microcontroller for digital controlled monitor with Universal Serial Bus (USB) interface

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WT62P1

Data Sheet Rev. 1.01



  







  

  



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Fig. 1 Reset Signals

External Reset

A low level on the RESET/3.3V pin will generate reset.

Illegal address Reset

When the address bus of CPU goes to illegal address, a reset pulse will be generated.

The illegal address is defined as $0040h~$007Fh, $0300h~$0FFEh and $1000h~$7FFFh.

Low VDD Voltage Reset

When VDD is below 3.9V, an internal reset signal is generated. The reset signal will last 2.048 ms after

the voltage is higher than 3.9V.

Watchdog Timer Reset

If a time-out happens when watchdog timer is enabled, a reset pulse is generated. Please refer

watchdog timer section for more information.

Weltrend Semiconductor, Inc.

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