GS840H18T-150 Ver la hoja de datos (PDF) - Giga Semiconductor

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GS840H18T-150

256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs

Giga Semiconductor 

GS840H18/32/36T/B-180/166/150/100

BGA Pin Description

Pin Location

N4, P4

A2, A3, A5, A6, B3, B5, C2, C3, C5,

C6, R2, R6, T3, T5

T4

T2, T6

T2, T6

K7, K6, L7, L6, M6, N7, N6, P7

H7, H6, G7, G6, F6, E7, E6, D7

H1, H2, G1, G2, F2, E1, E2, D1

K1, K2, L1, L2, M2, N1, N2, P1

P6, D6, D2, P2

P6, D6, D2, P2

L5, G5, G3, L3

P7, N6, L6, K7, H6, G7, F6, E7, D6

D1, E2, G2, H1, K2, L1, M2, N1, P2

L5, G3

B1, C1, R1, T1, U2, J3, U3, D4, L4,

U4, J5, U5, U6, B7, C7, R7

P6, N7, M6, L7, K6, H7, G6, E6, D7,

D2, B1, E1, F2, G1, H2, K1, L2, N2,

P1, G5, L3, T4

K4

M4

H4

E4, B6

B2

F4

G4

A4, B4

T7

R5

R3

J2, C4, J4, R4, J6

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

Symbol

A0, A1

An

An

NC

An

DQA1-DQA8

DQB1-DQB8

DQC1-DQC8

DQD1-DQD8

DQA9, DQB9,

DQC9, DQD9

NC

BA, BB, BC, BD

DQA1-DQA9

DQB1-DQB9

BA, BB

NC

NC

CK

BW

GW

E1, E3

E2

G

ADV

ADSP, ADSC

ZZ

FT

LBO

VDD

VSS

VDDQ

Type

I

I

-

I

I/O

I/O

-

I

I/O

I

-

-

I

I

I

I

I

I

I

I

I

I

I

I

I

I

Description

Address field LSB’s and Address Counter Preset Inputs.

Address Inputs

Address Input (x32/36 Versions)

No Connect (x32/36 Versions)

Address Input (x18 Version)

Data Input and Output pins. (x32/36 Versions)

Data Input and Output pins. (x36 Version)

No Connect (x32 Version)

Byte Write Enable for DQA, DQB, DQC, DQD I/O’s. Active Low. ( x36 Version)

Data Input and Output pins. (x18 Version)

Byte Write Enable for DQA, DQB I/O’s. Active Low. ( x18 Version)

No Connect

No Connect (x18 Version)

Clock Input Signal. Active High.

Byte Write. Writes all enabled bytes. Active Low.

Global Write Enable. Writes all bytes. Active Low.

Chip Enable. Active Low.

Chip Enable. Active High.

Output Enable. Active Low.

Burst address counter advance enable. Active Low.

Address Strobe (Processor, Cache Controller). Active Low.

Sleep Mode control. Active High.

Flow Through or Pipeline mode. Active Low.

Linear Burst Order mode. Active Low.

Core power supply.

I/O and Core Ground.

Output driver power supply.

Rev: 2.04 6/2000

9/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

© 1999, Giga Semiconductor, Inc.

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