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GS842Z18AB-166

4Mb Pipelined and Flow Through Synchronous NBT SRAMs

Giga Semiconductor 

Burst Counter Sequences

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

00

01

10

11

2nd address

01

10

11

00

3rd address

10

11

00

01

4th address

11

00

01

10

Note:

The burst counter wraps to initial state on the 5th clock.

GS842Z18/36AB-180/166/150/100

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

00

01

10

11

2nd address

01

00

11

10

3rd address

10

11

00

01

4th address

11

10

01

00

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

8

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after 2 cycles of wake up time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tKH

tKC

tKL

CK

tZZS

tZZH

tZZR

ZZ

Designing for Compatibility

The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal

found on Bump R5. Not all vendors offer this option, however, most mark Bump R5 as VDD or VDDQ on pipelined parts and VSS

on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.

Rev: 1.03 11/2004

11/30

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2001, GSI Technology

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