ML4900CS Ver la hoja de datos (PDF) - Micro Linear Corporation
Número de pieza
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ML4900CS Datasheet PDF : 8 Pages
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ML4900
PIN CONFIGURATION
ML4900
16-Pin Narrow SOIC (S16N)
D0
D1
D2
D3
SHDN
PWR GOOD
VREF
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
TOP VIEW
PROTECT
VDD
N DRV H
N DRV L
PWR GND
COMP
ISENSE
VFB
D0
D1
D2
D3
NC
SHDN
NC
PWR GOOD
VREF
GND
ML4900
20-Pin TSSOP (T20)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
TOP VIEW
PROTECT
VDD
NC
N DRV H
N DRV L
PWR GND
NC
COMP
ISENSE
VFB
PIN DESCRIPTION (Pin Number in Parentheses is for TSSOP Version)
PIN
1 (1)
NAME
D0
FUNCTION
LSB input to the DAC which sets
the output voltage
2 (2) D1
Input to the DAC which sets the
output voltage
3 (3) D2
Input to the DAC which sets the
output voltage
4 (4) D3
MSB input to the DAC which sets
the output voltage
5 (6) SHDN
Grounding this pin shuts down the
regulator
6 (8) PWR GOOD This open collector output goes
low whenever SHDN goes low or
when the output is not within
+10% of its nominal value
7 (9) VREF
Bypass connection for the internal
3.5V reference
PIN NAME
8 (10) GND
9 (11) VFB
10 (12) ISENSE
11 (13) COMP
12 (15) PWR GND
13 (16) N DRV L
14 (17) N DRV H
15 (19) VDD
16 (20) PROTECT
FUNCTION
Analog signal ground
Output voltage feedback pin
Current sense input
Connection for the compensation
and optional soft-start delay
network
Power ground
Synchronous rectifier driver output
Buck switch driver output
12V power supply input
Connection for the integrating
current limit network and the
UVLO monitor for the 5V supply
2
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