V53C518165A Ver la hoja de datos (PDF) - Mosel Vitelic, Corp
Número de pieza
componentes Descripción
Lista de partido
V53C518165A Datasheet PDF : 28 Pages
| |||
MOSEL VITELIC
V53C518165A
Notes:
1. All voltage are referenced to VSS.
2. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
3. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during
an EDO page mode cycle.
5. An initial pause of 200 ms is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of
8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6. AC measurements assume tT = 2ns.
7. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8. Measured with the specified current load and 100pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by
the latter of tRAC, tCAC, tCAA, tCPA, tOAC, tCAC is measured from tristate.
9. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.
10. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA.
11. Either tRCH or tRRH must be satisfied for a read cycle.
12. tOFF (max.), tOEZ (max.) define the time at which the outputs acheive the open-circuit condition and are not referenced
to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
13. Either tDZC or tDZO must be satisfied.
14. Either tCDD or tODD must be satisfied.
15. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electri-
cal characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit
(high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), and tAWD > tAWD (min.), the cycle
is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of con-
ditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16. These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in
read-write cycles.
17. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM oper-
ation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh
interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit
from Self Refresh.
V53C518165A Rev. 1.1 January 1998
8
Share Link: 