CDP1854A3 Ver la hoja de datos (PDF) - Intersil

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CDP1854A3

High Reliability CMOS Programmable Universal Asynchronous Receiver/Transmitter (UART)

Intersil 

CDP1854A/3, CDP1854AC/3

TRANSMITTER HOLDING

REGISTER LOADED

(NOTE 1)

T CLOCK

WRITE (TPB)

(NOTE 3)

THRE

SDO

tTT

tTTH

TRANSMITTER SHIFT

REGISTER LOADED

(NOTE 2)

tCC

tCH

tCL

1 2 3 4 5 6 7 14 15 16 1 2 3 4

tCD

tCTH

tCD

1ST DATA BIT

NOTES:

1. The holding register is loaded on the trailing edge of TPB.

2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTC

after the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + tCD later.

3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0

FIGURE 1. TRANSMITTER TIMING DIAGRAM - MODE 1

tCC

tCH

tCL

CLOCK 7 1/2

SAMPLE

CLOCK 7 1/2 LOAD

HOLDING REGISTER

R CLOCK

tDC

(NOTE 1)

SDI

1 2 3 4 5 6 7 16 1 2 3 4 5 6 7 8 9

START BIT

tTDA

PARITY

STOP BIT 1

tCDA

DA

READ

(NOTE 2)

tTT

TPB

OE

(NOTE 3)

PE

(NOTE 3)

FE

tCOE

tCPE

tCFE

NOTES:

1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next

high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.

2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the receiver holding register

by the time a new word is loaded into the receiver holding register, the OE signal will come true.

3. OE and PE share terminal 15 and are also available as two separate bits in the status register.

FIGURE 2. MODE 1 RECEIVER TIMING DIAGRAM

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