GS880Z18AT-133 Ver la hoja de datos (PDF) - Unspecified

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GS880Z18AT-133

9Mb Pipelined and Flow Through Synchronous NBT SRAM

Unspecified 

AC Test Conditions

Parameter

Conditions

Input high level

VDD – 0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

VDD/2

Output reference level

VDDQ/2

Output load

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

GS880Z18/36AT-250/225/200/166/150/133

DC Electrical Characteristics

Parameter

Input Leakage Current

(except mode pins)

ZZ Input Current

FT Input Current

Output Leakage Current

Output High Voltage

Output High Voltage

Output Low Voltage

Output Load 1

DQ

50Ω

30pF*

VDDQ/2

* Distributed Test Jig Capacitance

Symbol

IIL

IIN1

IIN2

IOL

VOH2

VOH3

VOL

Test Conditions

VIN = 0 to VDD

VDD ≥ VIN ≥ VIH

0 V ≤ VIN ≤ VIH

VDD ≥ VIN ≥ VIL

0 V ≤ VIN ≤ VIL

Output Disable, VOUT = 0 to VDD

IOH = –8 mA, VDDQ = 2.375 V

IOH = –8 mA, VDDQ = 3.135 V

IOL = 8 mA

Min

–1 uA

–1 uA

–1 uA

–100 uA

–1 uA

–1 uA

1.7 V

2.4 V

—

Max

1 uA

1 uA

100 uA

1 uA

1 uA

1 uA

—

—

0.4 V

Rev: 1.02 9/2002

16/25

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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