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PI6C2308A Datasheet PDF : 10 Pages
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PI6C2308A
3.3V Zero Delay Buffer 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Switching Characteristics(5,6) for Commercial Temperature Device
Parame te rs
Name
Test Conditions
FCLK
Output Frequency
Duty Cycle(5) = t2 ÷ t1
15pF to 30pF load
Measured at VDD/2
t2
Duty Cycle(5) = t2 ÷ t1 (-1H)
Measured at 1.4V,
FOUT ≤45 MHz
Duty Cycle = t2 ÷ t1 (-1,-2,-3,-4,-6)
Measured at 1.4V
t3
Rise Time(5) @30pF
t3
Rise Time(5) @15pF
t3
Rise Time(5) @30pF (-1H)
t4
Fall Time(5) @30pF
Measured between
0.8V and 2.0V
t4
Fall Time(5) @15pF
t4
Fall Time(5) @30pF (-1H)
t5
Output to Output Skew(5)
same bank
All outputs equally loaded, VDD/2
t5
Output to Output Skew(5)
different bank (2,3,6)
All outputs equally loaded, VDD/2
t6
Delay, REF Rising Edge to
FBK Rising Edge(5)
Measured at VDD/2
t7
Device to Device Skew(5)
Measured at VDD/2 on the
FBK pins of devices
t8
Output Slew Rate(5)
Measured between 0.8V and 2.0V
on -1H device using
Test Circuit #2
tJ
Cycle to Cycle Jitter(5)
Measured at 66.67 MHz,
loaded outputs
tLOCK
PLL Lock Time(5)
Stable power supply, valid clocks
presented on REF and FBK pins
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. REF and FBK inputs have a threshhold voltage of VDD/2.
5. Parameter is guaranteed by design and characterization. Not 100% tested in production.
6. For definition of t1-8, see Switching Waveforms on page 6
Min. Typ. Max. Units
10
140 MHz
45
50
55
45
50
55
%
40
50
60
2.2
1.5
1.5
ns
2.2
1.5
1.25
200
400
ps
0 ±150
0
500
1
V/ns
200 ps
1.0 ms
5
PS8385B 08/03/00
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