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HEF4541B Datasheet PDF : 17 Pages
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NXP Semiconductors
HEF4541B
Programmable timer
6. Functional description
Table 3. Function table[1]
Input
AR
MR
PH
H
L
X
L
L
X
X
H
X
X
L
X
X
L
X
X
L
L
X
L
H
MODE
X
X
X
H
L
X
X
MODE
auto reset disabled
auto reset enabled[2]
master reset active
normal operation selected division to output
single-cycle mode[3]
output initially LOW after reset
output initially HIGH, after reset
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
[2] For correct power-on reset, the supply voltage should be above 8.5 V. For VDD < 8.5 V, disable the autoreset and connect AR to VDD.
[3] The timer is initialized on a reset pulse and the output changes state after 2n-1 counts and remains in that state (latched). Reset of this
latch is obtained by master reset or by a LOW to HIGH transition on the MODE input.
Table 4. Frequency selection table
A0
A1
L
L
L
H
H
L
H
H
Number of counter stages n
13
10
8
16
f--O----S--C-
=
n
2
fO
8192
1024
256
65536
7. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDD
IIK
VI
IOK
II/O
Tstg
Tamb
Ptot
supply voltage
input clamping current
input voltage
output clamping current
input/output current
storage temperature
ambient temperature
total power dissipation
VI < −0.5 V or VI > VDD + 0.5 V
VO < −0.5 V or VO > VDD + 0.5 V
O output
Tamb = −40 °C to +85 °C
DIP14 package
SO14 package
P
power dissipation
Min
−0.5
-
−0.5
-
-
−65
−40
[1] -
[2] -
-
[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C.
HEF4541B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 June 2012
Max
Unit
+18
V
±10
mA
VDD + 0.5 V
±10
mA
±10
mA
+150
°C
+85
°C
750
mW
500
mW
100
mW
© NXP B.V. 2012. All rights reserved.
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