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ST75C530

SUPER INTEGRATED DEVICES WITH DSP, AFE & MEMORIES FORTELEPHONY, MODEM, FAX OVERINTERNET & POTS LINES

STMicroelectronics 

ST75C530 - ST75C540

V - FUNCTIONAL DESCRIPTION (continued)

Figure 7 : SPK1 Distortion versus RxA

Rx Softclipping and Distortion

(mVRMS)

103

D (%)

12

10

8

102

6

VSPK1 (VRMS)

4

Distortion

2

0

10

102

103

VMIC2 (mVRMS)

Figure 8 : Speaker and Line Tx Power Spectrums

POWER SPEC1

POWER SPEC2

0.0

0.0

64Avg

64Avg

0%Ovlp Ftop

0%Ovlp Ftop

dBm

RMS

V2

dB

RMS

Vv2

-80.0

-80.0

Speaker Output

Line Tx

Fxd Y O

Hz

5k

Note : Acoustic echo from speaker to microphone input with no

local speech. Receiving speech on line input.

Figure 9

GIO0[x]

V.3.13 - Low Power Mode

Sleep state can be attained by a SLEEPcommand.

When in sleep mode, the dual port RAM is unavail-

able and the clocks are disabled.

Wh en e ntering th e lo w p ower mod e, th e

ST75C530/540stops its oscillator, all the peripher-

als of the DSP core are stopped in order to reduce

the power consumption. The dual port RAM is

made inaccessible.

The ST75C530/540 can be awakened by a hard-

ware reset, a RING signal or a dummy write at any

location in the dual port RAM.

There is a maximum time of 20ms to restart the

oscillator after waking up and an additional 5ms

after the interrupt to be able to accept any com-

mand coming from the host.

V.3.14 - Reset

After a hardware reset, or an INIT command, the

ST75C530/540 clears all its internal memories,

clears the whole dual port RAM and starts to initial-

ize the delta sigma analog converters. As soon as

these initializations are completed, the

ST75C530/540 generates an interrupt IT6 (com-

mand acknoledge) and is programmed to send and

receive tones, the sample clock are programmed to

9600Hz. The total duration of the reset sequence is

about 5ms. After that time the ST75C530/540 is

readyto executecommands sent by the host micro-

controller. The duration of the reset signalshould be

greater than 700ns.

V.4 - Modem Interface

V.4.1 - Analog Interface

Refer to Block Diagram on page 7.

V.4.2 - General I/O and Relay Interface

16 pins are dedicated to the general I/O port. Two

are dedicatedto Relaydriver. The equivalent sche-

matic is as follows : see Figure 9.

RELAY[y]

IODIR0[x]

IODATA0[x]

(write)

DQ

IORELAY[y]

(write)

DQ

N

IODATA0[x]

(read)

18/84

IORELAY[y]

(read)

RGND

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