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V61C518256-10N

32K X 8 HIGH SPEED STATIC RAM

Mosel Vitelic, Corp 

MOSEL VITELIC

V61C518256

Data Retention Characteristics

Symbol Parameter

VDR

ICCDR

VCC for Data Retention

CE ³ VCC – 0.2V

Data Retention Current

VDR = 3.0V, CE ³ VDR – 0.2V

Com’l

Ind.

tCDR

Chip Deselect to Data Retention Time

tR

Operation Recovery Time (see Retention Waveform)

NOTES:

1. tRC = Read Cycle Time

2. TA = +25°C.

Low VCC Data Retention Waveform

Data Retention Mode

Min.

2.0

—

—

0

tRC(1)

VCC

4.5V

VDR ³ 2V

4.5V

tCDR

tR

CE

2.2V

VDR

2.2V

Typ.(2)

—

—

—

—

—

Max.

5.5

150

200

—

—

518256-07

Units

V

mA

ns

ns

AC Test Conditions

Key to Switching Waveforms

Input Pulse Levels

Input Rise and Fall Times

Timing Reference Levels

Output Load

0 to 3V

3 ns

1.5V

see below

AC Test Loads and Waveforms

I/O Pin

+5V

480 ½

255 ½

CL = 30 pF*

WAVEFORM

INPUTS

OUTPUTS

MUST BE

STEADY

WILL BE

STEADY

MAY CHANGE

FROM H TO L

WILL BE

CHANGING

FROM H TO L

MAY CHANGE

FROM L TO H

WILL BE

CHANGING

FROM L TO H

DON'T CARE:

ANY CHANGE

PERMITTED

DOES NOT

APPLY

CHANGING:

STATE

UNKNOWN

CENTER

LINE IS HIGH

IMPEDANCE

“OFF” STATE

* Includes scope and jig capacitance

+5V

I/O Pin

480 ½

255 ½

5 pF*

Output load for tCLZ, tCHZ, tOHZ, tOLZ, tWZ, tOW

518256-06

V61C518256 Rev. 0.3 July 1998

5

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