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PCK2057DGG Datasheet PDF : 13 Pages
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Philips Semiconductors
70 – 190 MHz I2C differential 1:10 clock driver
Product data
PCK2057
AC CHARACTERISTICS
SYMBOL
PARAMETER
tPD
tPHL
ten
tdis
tjit(per)
tjit(cc)
tjit(hper)
Propagation delay time
HIGH-to-LOW level propagation delay time
Output enable time
Output disable time
Jitter (period); see Figure 4
Jitter (cycle-to-cycle); see Figure 5
Half-period jitter; see Figure 6
t∅
Static phase offset; see Figure 1
tslr(o)
tsk(o)
Output clock slew rate; see Figure 3
Output skew; see Figure 2
SSC modulation frequency
SSC clock input frequency deviation
NOTE:
1. This time is for a PLL frequency of 100 MHz.
AC WAVEFORMS
CLK
CLK
TEST CONDITIONS
Test mode/CLK to any output
SCL to SDA (acknowledge)
Test mode/SDA to Y output
Test mode/SDA to Y output
100 MHz to 167 MHz
100 MHz to 167 MHz
100 MHz to 167 MHz
133 MHz/VID on CLK = 0.71 V
167 MHz/VID on CLK = 0.71 V
terminated with 120 Ω/14 pF
LIMITS
MIN
TYP MAX
—
3.7
—
—
500 1
—
—
85
—
—
35
—
–75
—
75
–75
—
75
–90
—
90
220
—
450
140
—
270
1
—
2
—
—
75
30
—
33.3
0.00
—
–0.50
UNIT
ns
ns
ns
ns
ps
ps
ps
ps
ps
V/ns
ps
kHz
%
FBIN
FBIN
t(O)n
Σ t(O) =
n =N
1
t(O)n
N
t(O)n + 1
(N is a large number of samples)
SW00882
Figure 1. Static phase offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(O)
Figure 2. Output skew
SW00883
2001 Jun 12
8
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