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V53C517405A

4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM

Mosel Vitelic, Corp 

MOSEL VITELIC

V53C517405A

DC and Operating Characteristics (1-2)

TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, tT = 2ns, unless otherwise specified.

Symbol

Parameter

Access

V53C517405A

Time Min. Typ. Max. Unit

Test Conditions

ILI

Input Leakage Current

(any input pin)

–10

10 µA

VSS ≤ VIN ≤ VCC + 0.5V

ILO

Output Leakage Current

–10

(for High-Z State)

ICC1

VCC Supply Current,

50

Operating

60

10 µA

80 mA

70

VSS ≤ VOUT ≤ VCC + 0.5V

RAS, CAS at VIH

other input ≥ VSS

tRC = tRC (min.)

ICC2

VCC Supply Current,

TTL Standby

ICC3

VCC Supply Current,

50

RAS-Only Refresh

60

2 mA

80 mA

70

RAS, CAS at VIH

other inputs ≥ VSS

tRC = tRC (min.)

ICC4

VCC Supply Current,

50

EDO Page Mode

Operation

60

35 mA

30

Minimum Cycle

ICC5

VCC Supply Current,

50

during CAS-before-RAS

Refresh

60

70

120 mA

110

100

ICC6

VCC Supply Current,

CMOS Standby

VCC

Power Supply Voltage

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

4.5

–0.5

2.4

2.4

1.0 mA

5.0

5.5 V

0.8 V

VCC+0.5 V

0.4 V

V

RAS ≥ VCC – 0.2 V,

CAS ≥ VCC – 0.2 V

other input ≥ VSS

IOL = 4.2 mA

IOH = –5 mA

Notes

1

1

2, 3, 4

2, 4

2, 3, 4

2, 4

1

1

1

1

1

V53C517405A Rev. 1.1 March 1998

4

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