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EP7309-IB-C

High-Performance, Low-Power System on Chip Enhanced Digital Audio Interface

Cirrus Logic 

EP7309

High-Performance, Low-Power System on Chip

Timings

Timing Diagram Conventions

This data sheet contains one or more timing diagrams. The following key explains the components used in these

diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached

unless specifically stated.

Clock

High to Low

High/Low to High

Bus Change

Bus Valid

Undefined/Invalid

Valid Bus to Tristate

Bus/Signal Omission

Timing Conditions

Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are

specified at VDD = 2.3 - 2.7 V and VSS = 0 V over an operating temperature of 0°C to +70°C. Those characteristics

marked with a # will be significantly different for 13 MHz mode because the EXPCLK is provided as an input rather

than generated internally. These timings are estimated at present. The timing values are referenced to 1/2 VDD.

DS507PP1

Copyright 2001 Cirrus Logic (All Rights Reserved)

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