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EP7309-EB-C

High-Performance, Low-Power System on Chip Enhanced Digital Audio Interface

Cirrus Logic 

Static Memory Single Read Cycle

EP7309

High-Performance, Low-Power System on Chip

EXPCLK

nCS

A

nMWE

nMOE

HALF

WORD

WORD

D

EXPRDY

WRITE

tCSd

tAd

tCSh

tHWd

tWDd

tMOEd

tWRd

tEXs

tMOEh

tDs

tDh

tEXh

Figure 2. Static Memory Single Read Cycle Timing Measurement

Note:

1. The cycle time can be extended by integer multiples of the clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and

77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on

the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where

EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

DS507PP1

Copyright 2001 Cirrus Logic (All Rights Reserved)

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