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EP7312-EV

High-Performance, Low-Power System on Chip with SDRAM and Enhanced Digital Audio Interface

Cirrus Logic 

EP7312

High-Performance, Low-Power System on Chip

Timings

Timing Diagram Conventions

This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any

variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless

specifically stated.

C lo c k

H ig h to L o w

H ig h /L o w to H ig h

B us C hange

B u s V a lid

U n d e fin e d /In v a lid

V a lid B u s to T r is ta te

B u s /S ig n a l O m is s io n

Figure 2. Legend for Timing Diagrams

Timing Conditions

Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are

specified at VDDIO = 3.1 - 3.5 V and VSS = 0 V over an operating temperature of -40°C to +85°C. Pin loadings is 50 pF.

The timing values are referenced to 1/2 VDD.

DS508PP5

©Copyright Cirrus Logic, Inc. 2003

(All Rights Reserved)

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