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EP7312-EB

High-Performance, Low-Power System on Chip with SDRAM and Enhanced Digital Audio Interface

Cirrus Logic 

EP7312

High-Performance, Low-Power System on Chip

SDRAM Burst Read Cycle

SDCLK

SDCS

SDRAS

SDCAS

ADDR

DATA

SDQM

[0:3]

SDMWE

tCSa

tCSd

tRAa

tRAd

tADv

ADRAS

tCSa

tCSd

tCAa

tCAd

tADv

tRAnv

ADCAS

tDAs

tDAs

D1

tDAh

D2

tDAh

tDAs

D3

tDAh

tDAs

D4

tDAh

Figure 4. SDRAM Burst Read Cycle Timing Measurement

Note: 1. Timings are shown with CAS latency = 2

2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal.

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©Copyright Cirrus Logic, Inc. 2003

(All Rights Reserved)

DS508PP5

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