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EP7312-ER

High-Performance, Low-Power System on Chip with SDRAM and Enhanced Digital Audio Interface

Cirrus Logic 

SDRAM Burst Write Cycle

EP7312

High-Performance, Low-Power System on Chip

SDCLK

SDCS

tRAa

SDRAS

SDCAS

ADDR

DATA

SDQM

SDMWE

tCSa

tCSd

tCSa

tCSd

tRAd

tCAa

tCAd

tADv

tADv

ADRAS

ADCAS

tDAd

tDAd

tDAd

tDAd

D1

D2

D3

D4

0

tMWa

tMWd

Figure 5. SDRAM Burst Write Cycle Timing Measurement

Note:

1. Timings are shown with CAS latency = 2

2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal

DS508PP5

©Copyright Cirrus Logic, Inc. 2003

(All Rights Reserved)

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