IDT54821ATEB Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT54821ATEB Datasheet PDF : 9 Pages
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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
FUNCTION TABLE(1)
Names
DI
CLR
CP
YI
EN
OE
I/O
Description
Inputs
I
The D flip-flop data inputs.
I
When the clear input is LOW and OE is
LOW, the QI outputs are LOW. When
the clear input is HIGH, data can be
OE
CLR
EN
DI
CP
H
H
L
L
↑
H
H
L
H
↑
entered into the register.
H
L
X
X
X
I
Clock Pulse for the Register; enters
L
L
X
X
X
data into the register on the LOW-to-
H
H
H
X
X
HIGH transition.
L
H
H
X
X
O The register 3-state outputs.
H
H
L
L
↑
I
Clock Enable. When the clock enable is
LOW, data on the D I input is transferred
to the QI output on the LOW-to-HIGH
H
H
L
H
↑
L
H
L
L
↑
L
H
L
H
↑
clock transition. When the clock enable
is HIGH, the QI outputs do not change
state, regardless of the data or clock
NOTE:
1. H = HIGH
L = LOW
X = Don’t Care
input transitions.
NC = No Change
I
Output Control. When the OE input is
↑ = LOW-to-HIGH Transition
HIGH, the Y I outputs are in the high-
Z = High Impedance
impedance state. When the OE input is
LOW, the TRUE register data is present
at the YI outputs.
2567 tbl 01
Internal/
Outputs
QI
YI
L
Z
H
Z
L
Z
L
L
NC Z
NC NC
L
Z
H
Z
L
L
H
H
Function
High Z
Clear
Hold
Load
2567 tbl 02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect to
GND
VTERM(3) Terminal Voltage
with Respect to
GND
TA
Operating
Temperature
TBIAS Temperature
Under Bias
TSTG Storage
Temperature
PT
Power Dissipation
Commercial
–0.5 to +7.0
–0.5 to
VCC +0.5
0 to +70
–55 to +125
–55 to +125
0.5
Military
–0.5 to +7.0
–0.5 to
VCC +0.5
–55 to +125
–65 to +135
–65 to +150
0.5
Unit
V
V
°C
°C
°C
W
IOUT
DC Output
–60 to +120 –60 to +120 mA
Current
NOTES:
2567 lnk 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN
Input
Capacitance
VIN = 0V
6
10 pF
COUT Output
VOUT = 0V 8
12 pF
Capacitance
NOTE:
2567 lnk 04
1. This parameter is measured at characterization but not tested.
6.21
3
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