IDT7027 Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT7027

HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7027S/L

High-Speed 32K x 16 Dual-Port Static RAM

Waveform of Read Cycles(5)

ADDR

CE(6)

OE

UB, LB

R/W

DATAOUT

BUSYOUT

tAA (4)

tACE (4)

tAOE (4)

tABE (4)

tLZ (1)

Military, Industrial and Commercial Temperature Ranges

tRC

(4)

VALID DATA

tBDD (3,4)

tOH

tHZ (2)

3199 drw 05

Timing of Power-Up Power-Down

CE(6)

tPU

ICC

50%

ISB

tPD

50%

3199 drw 06 .

NOTES:

1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

6. Refer to Chip Enable Truth Table.

6.842

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