SIC402A Ver la hoja de datos (PDF) - Vishay Semiconductors
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SIC402A
Vishay Semiconductors
SIC402A Datasheet PDF : 26 Pages
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www.vishay.com
SiC402A, SiC402BCD
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS UNLESS SPECIFIED
VIN = 12 V, TA = +25 °C for typ.,
-40 °C to +85 °C for min. and max.,
TJ = < 125 °C, VDD = +5 V,
typical application circuit
LIMITS
MIN. TYP.
MAX.
UNIT
Power Good
Power Good Threshold Voltage
Start-Up Delay Time
(between PWM enable and PGOOD high)
Fault (noise-immunity) Delay Time b
Leakage Current
Power Good On-Resistance
Fault Protection
Vally Current Limit c
ILIM Source Current
ILIM Comparator Offset Voltage
Output Under-Voltage Fault
Smart Power-Save Protection
Threshold b
Over-Voltage Protection Threshold
Over-Voltage Fault Delay b
Over Temperature Shutdown b
Logic Inputs / Outputs
PG_VTH_UPPER
PG_VTH_LOWER
PG_Td
PG_ICC
PG_ILK
PG_RDS-ON
ILIM
VILM-LK
VOUV_Fault
PSAVE_VTH
tOV-Delay
TShut
Upper limit, VFB > internal 600 mV
reference
Lower limit, VFB < internal 600 mV
reference
VDD = 5 V, Css = 10 nF
VDD = 3 V, Css = 10 nF
VDD = 5 V, RILIM = 4460,
TJ = 0 °C to +125 °C
VDD = 3 V, RILIM = 4460
With respect to AGND
VFB with respect to Internal 600 mV
reference, 8 consecutive clocks
VFB with respect to internal 600 mV
reference
VFB with respect to internal 600 mV
reference
10 °C hysteresis
-
+20
-
%
-
-10
-
-
12
-
ms
-
7
-
-
5
-
μs
-
-
1
μA
-
10
-
8.5
10 11.5
A
-
8.5
-
-
10
-
μA
-10
0
+10 mV
-
-25
-
-
+10
-
%
-
+20
-
-
5
-
μs
-
150
-
°C
Logic Input High Voltage
VIH
1
-
-
Logic Input Low Voltage
VIL
EN/PSV Input for PSAVE Operation b
EN/PSV Input for Forced Continuous
Operation b
VDD = 5 V
-
-
0.4
2.2
-
5
V
1
-
2
EN/PSV Input for Disabling Switcher
0
-
0.4
EN/PSV Input Bias Current
IEN
EN/PSV = VDD or AGND
-10
-
+10
ENL Input Bias Current
ENL = VIN = 28 V
-
10
18 μA
FBL, FB Input Bias Current
Linear Dropout Regulator
FBL_ILK
FBL, FB = VDD or AGND
-1
-
+1
FBL b
VLDO ACC
-
0.75
-
V
LDO Current Limit
LDO_ILIM
Short-circuit protection,
VIN =12 V, VDD < 0.75 V
Start-up and foldback, VIN = 12 V,
0.75 < VDD < 90 % of final VDD value
-
65
-
-
115
-
mA
VLDO to VOUT Switch-Over Threshold d
VLDO to VOUT Non-Switch-Over Threshold d
VLDO to VOUT Switch-Over Resistance
VLDO-BPS
VLDO-NBPS
RLDO
Operating current limit, VIN = 12 V,
VDD > 90 % of final VDD value
VOUT = 5 V
135 200
-
-130
-500
-
- +130
mV
- +500
2
-
LDO Drop Out Voltage e
From VIN to VDD, VDD = +5 V,
IVLDO = 100 mA
-
1.2
-
V
Notes
a. VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
b. Typical value measured on standard evaluation board.
c. SiC402A/B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout.
d. The switch-over threshold is the maximum voltage differential between the VDD and VOUT pins which ensures that VLDO will internally
VswLDitOchw-iollvneorttoswViOtcUhT-.oTvheer
non-switch-over
to VOUT.
threshold
is
the
minimum
voltage
differential
between
the
VLDO
and
VOUT
pins
which
ensures
that
e. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point.
S14-2048-Rev. C, 13-Oct-14
5
Document Number: 63729
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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