RS7112-LAN Ver la hoja de datos (PDF) - Conexant Systems

Número de pieza

componentes Descripción

Lista de partido

RS7112-LAN

Home Networking Physical Layer Device with Integrated Analog Front End Circuitry

Conexant Systems 

Home Networking PHY with Integrated AFE

Serial Peripheral Interface

The SPI provides a software interface for configuration and

status of the CN7221.

The SPI signals are composed of: HLAN_SPI_CLK,

HLAN_SPI_DOUT, HLAN_SPI_DIN, and HLAN_SPI_CS#.

Commands are issued to the device by asserting the

HLAN_SPI_CS# signal (active low), shifting in an eight-bit

opcode; if the operation is a read or a write, the opcode is

followed by an eight-bit register address. If the operation is

a write, the address is followed by an eight-bit data byte. If

the operation is a read, the HLAN_SPI_DOUT pin will shift

out an eight bit data byte representing the contents of the

register referenced by the address field. All commands

must be initiated with a high-to-low transition on the

HLAN_SPI_CS# pin. The device also may be commanded

to set or clear its WE flag. This flag is cleared upon reset,

and disables all write operations when in that state.

Opcodes are as follows:

0000 0110

0000 0100

0000 0011

0000 0010

SET WE

CLEAR WE

READ

WRITE

Timing for the various signals in SPI mode is defined in

Table 4 and in Figure 3.

The HLAN_SPI_DIN signal should not be changed until at

least 100ns after the rising edge of HLAN_SPI_CLK. In

other words, the HLAN_SPI_DIN signal has a hold time

constraint of 100ns past the rising edge of

HLAN_SPI_CLK.

LANfinity™ CN7221

Signal

HLAN_SPI_CLK

HLAN_SPI_DOUT

HLAN_SPI_DIN

HLAN_SPI_CS#

Table 3. SPI Signals

Description

Serial interface clock

Serial data output

Serial data input

Serial interface chip select (active low)

Mnemonic

TWIDTHclkl

TWIDTHclkh

TSETcsl

TSETcsh

TDLYsov

TDLYsoz

TSETsiv

Table 4. SPI Timing

Description

Min Max

Positive half-cycle 400

pulse width

Negative half-cycle 400

pulse width

CSN low to rising

50

clock edge

CSN high to rising 50

clock edge

Falling clock edge to

50

SO valid

Falling clock edge to

100

SO tri-state

SI valid to rising

50

clock edge

Units

ns

ns

ns

ns

ns

ns

ns

CLK

TW IDTHclkl

TW IDTHclkh

TSETcsl

TSETcsh

CSN

TSETsiv

HLAN_SPI_DIN

HLAN_SPI_DOU

T

b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

Instruction Byte

Address Byte Data Byte (don't-care when reading)

TDLYsov

TDLYsoz

b7 b6 b5 b4 b3 b2 b1 b0

Data Byte (high-Z when writing)

Figure 3. SPI Timing

LAN-056, Rev. A

Conexant

9

PROPRIETARY INFORMATION

Share Link: