SMC91C100 Ver la hoja de datos (PDF) - SMSC -> Microchip

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SMC91C100

FEAST™ Fast Ethernet Controller

SMSC -> Microchip 

I/O SPACE - BANK1

OFFSET

NAME

TYPE

SYMBOL

2

BASE ADDRESS REGISTER

READ/WRITE

BAR

This register holds the I/O address decode option chosen for the SMC91C100. It is part of the EEPROM

saved setup, and is not usually modified during run-time.

HIGH

BYTE

A15

A14

A13

A9

A8

A7

A6

A5

0

0

0

1

1

0

0

0

LOW

BYTE

RESERVED

0

0

0

0

0

0

0

X

A15-A13 and A9-A5 These bits are compared

against the I/O address on the bus to determine

the IOBASE for the SMC91C100's registers. The

64k I/O space is fully decoded by the

SMC91C100 down to a 16 location space,

therefore, the unspecified address lines A4, A10,

A11 and A12 must be all zeros.

All bits in this register are loaded from the serial

EEPROM. The I/O base decode defaults to 300h

(namely, the high byte defaults to 18h).

30

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