SMC91C100 Ver la hoja de datos (PDF) - SMSC -> Microchip

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SMC91C100

FEAST™ Fast Ethernet Controller

SMSC -> Microchip 

Note: When an EEPROM access is in progress

the STORE and RELOAD bits will be read back

as high. The remaining 14 bits of this register

will be invalid. During this time attempted

read/write operations, other than polling the

EEPROM status, will NOT have any effect on

the internal registers. The CPU can resume

accesses to the SMC91C100 after both bits are

low. A worst case RELOAD operation initiated by

RESET or by software takes less than 750µsec.

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