TDA9332H/N2 Ver la hoja de datos (PDF) - Philips Electronics
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TDA9332H/N2 Datasheet PDF : 56 Pages
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Philips Semiconductors
I2C-bus controlled TV display processors
Preliminary specification
TDA933xH series
Via the I2C-bus, an adjustable offset can be made on the
black level of red and green channels with respect to the
level that is generated by the black current control loop.
These controls can be used to adjust the colour
temperature of the dark part of the picture, independent of
the white point adjustment.
When the TV receiver is switched on, the black current
stabilization circuit is directly activated and the RGB
outputs are blanked. The blanking is switched off as soon
as the loop has stabilized (e.g. the first time that bit BCF
changes from 1 to 0, see also Chapter “Characteristics”;
note 15). This ensures that the switch-on time is reduced
to a minimum and is only dependent on the warm-up time
of the picture tube.
The black current stabilization system checks the output
level of the three channels and indicates whether the black
level of the lowest RGB output of the IC is in a certain
window (WBC bit), below or above this window (HBC bit).
This indication can be read from the I2C-bus and can be
used for automatic adjustment of voltage Vg2 during the
production of the TV receiver.
When a failure occurs in the black current loop (e.g. due to
an open circuit), status bit BCF is set. This information can
be used to blank the picture tube to avoid damage to the
screen.
The control circuit contains an average beam current
limiting circuit and a peak white level (PWL) circuit. The
PWL detects small white areas in the picture that are not
detected by the average beam current limiter. The PWL
can be adjusted via the I2C-bus. A low-pass filter is placed
in front of the peak detector to prevent it from reacting to
short transients in the video signal. The capacitor of the
low-pass filter is connected externally so that the set
maker can adapt the time constant as required. The IC
also contains a soft clipper that limits the amplitude of the
short transients in the RGB output signals. In this way, spot
blooming on, for instance, subtitles is prevented. The
difference between the PWL and the soft clipping level can
be adjusted via the I2C-bus in a few steps.
The vertical blanking is adapted to the vertical frequency
of the incoming signal (50 or 100 Hz or, 60 or 120 Hz).
When the flyback time of the vertical output stage is
greater than the 60 Hz blanking time, the blanking can be
increased to the same value as that of the 50 Hz blanking.
This can be set by means of bit LBM.
When no video is available, it is possible to insert a blue
background. This feature can be activated via bit EBB.
Synchronization and deflection processing
HORIZONTAL SYNCHRONIZATION AND DRIVE CIRCUIT
The horizontal drive signal is obtained from an internal
VCO which runs at a frequency of 440 times (2fH mode) or
880 times (1fH mode) the frequency of the incoming HD
signal. The free-running frequency of this VCO is
calibrated by a crystal oscillator which needs an external
12 MHz crystal or ceramic resonator as a reference. It is
also possible to supply an external reference signal to the
IC (in this case, the external resonator should be
removed).
The VCO is synchronized to the incoming horizontal HD
pulse (applied from the feature box or the input processor)
by a PLL with an internal time constant. The frequency of
the horizontal drive signal (1fH or 2fH) is selected by means
of a switching pin, which must be connected to ground or
left open-circuit.
For HDTV applications, it is possible to change the
free-running frequency of the horizontal drive output. For
the 1080i-60 Hz scanning system the free-running
frequency can be increased to 33.8 kHz with the HDTV bit,
while for the 1080i-50 Hz system (China and Australia) the
free-running frequency can be decreased to 28.5 kHz with
the CDTV bit.
For safety reasons, switching between 1fH and 2fH
modes is only possible when the IC is in the standby
mode.
For the TDA9331H and TDA9332H, it is also possible to
set the horizontal PLL to a ‘multi-sync’ mode by means of
bit VGA. In this mode, the circuit detects the frequency of
the incoming sync pulses and adjusts the centre frequency
of the VCO accordingly by means of an internal
Digital-to-Analog-Converter (DAC). The frequency range
in this mode is 30 to 50 kHz at the output.
The polarities of the incoming HD and VD pulses are
detected internally. The detected polarity can be read out
via status bits HPOL and VPOL.
The horizontal drive signal is generated by a second
control loop which compares the phase of the reference
signal (applied from the internal VCO) with the flyback
pulse. The time constant of this loop is set internally. The
IC has a dynamic horizontal phase correction input, which
can be used to compensate phase shifts that are caused
by beam current variations. Additional settings of the
horizontal deflection (which are realized via the second
loop) are the horizontal shift and horizontal parallelogram
and bow corrections (see Chapter “Characteristics”;
Fig.16). The adjustments are realized via the I2C-bus.
2002 Jun 04
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