CXD1948R Ver la hoja de datos (PDF) - Sony Semiconductor

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CXD1948R

IEEE1394 Link Layer LSI for DVB and DSS

Sony Semiconductor 

Pin

No.

Symbol

I/O

Description

35 ADDRESS2 I Host I/F address bus BIT 2

36 ADDRESS1 I Host I/F address bus BIT 1

37 ADDRESS0 I Host I/F address bus BIT 0

38 VDD

— Power supply

39 XCS

I

Host I/F chip select signal

0: Active; 1: Non-active

40 XWAIT

O

Host I/F wait signal

0: Active; 1: Non-active

41 XW/R

I

Host I/F write/read signal

0: Write; 1: Read

42 XINT

43 TEST8

O

Host I/F interrupt signal

0: Active; 1: Non-active

— Test pin∗

44 PORT0

I/O Parallel I/O port BIT0

45 PORT1

I/O Parallel I/O port BIT1

46 PORT2

47 TEST12

48 TEST13

I/O Parallel I/O port BIT2

— Test pin∗

— Test pin∗

49 VSS

50 TEST14

— GND

— Test pin∗

51 VDD

— Power supply

52 SYSCLK

I Phy I/F system clock (49.152MHz)

53 VSS

54 TEST15

55 TEST16

56 TEST17

57 TEST18

— GND

— Test pin∗

— Test pin∗

— Test pin∗

— Test pin∗

58 D3

I/O Phy I/F data bus BIT 3

59 D2

I/O Phy I/F data bus BIT 2

60 D1

I/O Phy I/F data bus BIT 1

61 D0

I/O Phy I/F data bus BIT 0

62 VSS

— GND

63 CTL1

I/O Phy I/F control bus BIT 1

64 CTL0

I/O Phy I/F control bus BIT 0

65 LREQ

O Phy I/F request signal

66 VDD

— Power supply

67 LPS

O Phy I/F Link power status signal

68 TEST19

— Test pin∗

∗ The test pins should be used open.

–6–

CXD1948R

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