MAX2023EVKIT Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Lista de partido

MAX2023EVKIT

MAX2023 Evaluation Kit

Maxim Integrated 

MAX2023 Evaluation Kit

C = 2.2pF

I

L = 11nH

C = 2.2pF

50Ω

50Ω C = 2.2pF

MAX2023

RF MODULATOR

LO

90°

RF

50Ω

Q

L = 11nH

50Ω C = 2.2pF

Figure 1. Example Diplexer Network for GSM 1800/1900 Applications

As shown in Figure 1, providing an RC termination on

each of the I+, I-, Q+, Q- ports reduces the amount of

LO leakage present at the RF port under varying temp-

erature, LO frequency, and baseband drive conditions.

Note that the resistor value is chosen to be 50Ω with a

corner frequency 1 / (2πRC) selected to adequately filter

the fLO and 2fLO leakage, yet not affecting the flatness

of the baseband response at the highest baseband

frequency. The common-mode fLO and 2fLO signals at

I+/I- and Q+/Q- effectively see the RC networks and

thus become terminated in 25Ω (R/2). The RC network

provides a path for absorbing the 2fLO and fLO leakage,

while the inductor provides high impedance at fLO and

2fLO to help the diplexing process.

The MAX2023 EV kit includes flexibility for a diplexer

network to be installed if desired. See Figure 3 for

details on the EV kit schematic.

Layout Considerations

The MAX2023 evaluation board can be a guide for your

board layout. Pay close attention to thermal design and

close placement of components to the IC. The

MAX2023 package’s exposed paddle (EP) conducts

heat from the device and provides a low-impedance

electrical connection to the ground plane. The EP must

be attached to the PCB ground plane with a low ther-

mal and electrical impedance contact. Ideally, this is

achieved by soldering the backside of the package

directly to a top metal ground plane on the PCB.

Alternatively, the EP can be connected to an internal or

bottom-side ground plane using an array of plated vias

directly below the EP. The MAX2023 EV kit uses nine

evenly spaced 0.016in-diameter, plated through holes

to connect the EP to the lower ground planes.

Depending on the ground plane spacing, large sur-

face-mount pads in the IF path may need to have the

ground plane relieved under them to reduce parasitic

shunt capacitance.

4 _______________________________________________________________________________________

Share Link: