GF9105ACQQ Ver la hoja de datos (PDF) - Unspecified
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GF9105ACQQ Datasheet PDF : 37 Pages
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GF9105A OPERATION IN DECIMATION MODE (INT/DEC=0)
Refer to Figure 5b for a functional block diagram of the GF9105A operation with INT/DEC=0
BIT WEIGHTING
When using multiplexed input data, the Processing Core is limited to processing either 8-bit or 10-bit unsigned input data.
The input data should be embedded within the 13-bit data port as shown in the tables of the Bit Weighting subsection of the
Interpolation Mode Section. Note that when HVF_OUT=1, P112, P212 and P312 (which corresponds to b12) are outputs rather
than inputs. These 3 outputs are used for presenting H, V and F output signals. The user should be careful to ensure that
P112, P212 and P312 are not driven by upstream logic when HVF_OUT=1. Other unused inputs should be set low.
When using non-multiplexed input data, the GF9105A Processing Core can accept up to 13-bit two’s complement data from
Processing Core input ports C1-C3 and up to 11-bit two’s complement data from Processing Core input port C4. Note that
signed or unsigned numbers that fit within the relevant 13-bit or 11-bit dynamic range may also be presented to the device
inputs. This type of input data must still be formatted as a 13-bit or 11-bit two’s complement number, with appropriate sign
extensions. Input bit weighting is as shown below.
OUTPUT/INPUT = 0, HVF_OUT = 0
13 BIT PHYSICAL INTERFACE
DATA PORT REFERENCE
Input Port: P112..0 to P312..0
13 bit Two’s Complement input (10
bit based data)
b12
b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b12
b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Input Port: P112..0 to P312..0
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
11 bit Two’s Complement input (8 bit
based data)
Input Port: P410..0
11 bit Two’s Complement input (10
bit based data)
NA
NA b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Input Port: P410..0
9 bit unsigned input (8 bit based
data)
NA
NA
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
OUTPUT/INPUT = 0, HVF_OUT = 1
13 BIT PHYSICAL INTERFACE
DATA PORT REFERENCE
Output Port: P112 P212 or P312
b12
b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
H, V or F -
-
-
-
-
-
-
-
-
-
-
-
output
Input Port: P111..0 to P311..0
12 bit Two’s Complement input (10
bit based data)
-
b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Input Port: P111..0 to P311..0
-
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
10 bit Two’s Complement input (8 bit
based data)
Input Port: P410..0
11 bit Two’s Complement input (10
bit based data)
NA
NA b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Input Port: P410..0
9 bit unsigned input (8 bit based
data)
NA
NA
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
0
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