78Q2120 Ver la hoja de datos (PDF) - TDK Corporation
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78Q2120 Datasheet PDF : 33 Pages
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78Q2120
10/100BASE-TX
Ethernet Transceiver
MR16 - VENDOR SPECIFIC REGISTER
BIT
16.15
16.14
16.13
16.12
16.11
16.10
16.9
16.8
16.7
16.6
16.5
16.4
16.3:2
SYMBOL
RPTR
INT LEVEL
RSVD
TXHIM
SQE TEST
INHIBIT
10BT
NATURAL
LOOPBACK
GPIO1_DAT
GPIO1_DIR
GPIO0_DAT
GPIO0_DIR
APOL
RVSPOL
RSVD
TYPE
R, W, (0)
R, W, 0
R, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 0
R, W, 1
R, W, 0
R, W, 1
R, W, 0
R, (W), 0
R,W,0
DESCRIPTION
REPEATER MODE: When set, this bit puts the chip into repeater
mode. In this mode, full duplex is prohibited, CRS responds to
receive activity only and, in 10BASE-T mode, the SQE test function
is disabled.
When this bit is a zero, the INTR pin is forced low to signal an
interrupt. Setting this bit causes the INTR pin to be forced high to
signal an interrupt.
RESERVED
TRANSMIT HIGH IMPEDANCE: When this bit is set, the transmitter
UTP drivers are in a high impedance state and TXCLK is tri-stated.
The receive circuitry remains fully functional. Only a reset condition
will automatically clear this bit.
Setting this bit disables 10BASE-T SQE testing. By default, when
this bit is a zero, the SQE test is performed by generating a COL
pulse following the completion of a packet transmission.
Setting this bit causes transmitted data on TXD to be automatically
looped back to the RXD receive signals when 10BASE-T mode is
enabled.
GENERAL PURPOSE I/O 1 DATA BIT: When the GPIO_DIR is set,
this bit reflects the value of the GPIO1 pin. When the GPIO1_DIR is
reset, the value of this bit is driven onto the GPIO1 pin. (80-pin
TQFP only)
GENERAL PURPOSE I/O 1 DIRECTION BIT: Setting this bit
configures the GPIO1 pin as an input. Resetting configures GPOI_1
as an output. (80-pin TQFP only)
GENERAL PURPOSE I/O 0 DATA BIT: When the GPIO0_DIR is
set, this bit reflects the value of the GPIO0 pin. When the
GPIO0_DIR is reset, the value of this bit is driven onto the GPIO0
pin. (80-pin TQFP only)
GENERAL PURPOSE I/O 0 DIRECTION BIT: Setting this bit
configures the GPIO0 pin as an input. Resetting it configures GPIO0
as an output. (80-pin TQFP only)
AUTO POLARITY: During auto-negotiation and 10BASE-T mode,
the 78Q2120 is able to automatically invert the received signal - both
the Manchester data and link pulses - if necessary. Setting this bit
disables this feature.
REVERSE POLARITY: The reverse polarity is detected either
through 8 inverted 10BASE-T link pulses (NLP) or through one burst
of inverted fast link pulses (FLP). When the reverse polarity is
detected, the 78Q2120 will invert the receive data path and set this
bit to logic one if the feature is not disabled. If APOL is a logic 1,
then this bit is write-able. Setting this bit forces the polarity to be
reversed.
RESERVED. Must be zero.
15
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