MB86615 Ver la hoja de datos (PDF) - Fujitsu

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Lista de partido

MB86615

IEEE 1394 Bus Controller (for DVC)

Fujitsu 

MB86615

s BLOCK DIAGRAM

IDIR

ICLK

ILWRE

ID7 to ID0

IV

ICRCE

FP

ISO

sending

packet

processing

ISO

receiving

packet

processing

LINK

layer

control

circuit

PHY

layer

control

circuit

TPA

TPA

TPB

TPB

TPBIAS

CS

A5 to A1

D15 to D6, D0

AD5 to AD1

RD (R/W)

WR (DS)

ALE

INT

DREQ

DACK

ASYNC

send-only

FIFO

(128 byte)

ASYNC

sending

packet

processing

ASYNC

receive-only

FIFO

(128 byte)

ASYNC

receiving

packet

processing

Cycle master

Transaction

Dedicated transaction

control circuit block control circuit block

Register block

CSR

PLL circuit

12

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