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8574A Datasheet PDF : 33 Pages
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NXP Semiconductors
PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
7. Functional description
Refer to Figure 1 “Block diagram”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address format of the
PCF8574/74A is shown in Figure 6. Slave address pins A2, A1 and A0 are held HIGH or
LOW to choose one of eight slave addresses. To conserve power, no internal pull-up
resistors are incorporated on A2, A1 or A0, so they must be externally held HIGH or LOW.
The address pins (A2, A1, A0) can connect to VDD or VSS directly or through resistors.
slave address
R/W
slave address
R/W
0 1 0 0 A2 A1 A0 0
0 1 1 1 A2 A1 A0 0
fixed
hardware
selectable
002aad628
fixed
hardware
selectable
002aad629
a. PCF8574
b. PCF8574A
Fig 6. PCF8574 and PCF8574A slave addresses
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation (write operation is shown in
Figure 6).
7.1.1 Address maps
The PCF8574 and PCF8574A are functionally the same, but have a different fixed portion
(A6 to A3) of the slave address. This allows eight of the PCF8574 and eight of the
PCF8574A to be on the same I2C-bus without address conflict.
Table 4. PCF8574 address map
Pin connectivity
Address of PCF8574
Address byte value
7-bit
A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write
Read hexadecimal
address
without R/W
VSS VSS VSS 0 1 0 0 0 0 0 -
40h
41h
20h
VSS VSS VDD 0 1 0 0 0 0 1 -
42h
43h
21h
VSS VDD VSS 0 1 0 0 0 1 0 -
44h
45h
22h
VSS VDD VDD 0 1 0 0 0 1 1 -
46h
47h
23h
VDD VSS VSS 0 1 0 0 1 0 0 -
48h
49h
24h
VDD VSS VDD 0 1 0 0 1 0 1 -
4Ah
4Bh
25h
VDD VDD VSS 0 1 0 0 1 1 0 -
4Ch
4Dh
26h
VDD VDD VDD 0 1 0 0 1 1 1 -
4Eh
4Fh
27h
PCF8574_PCF8574A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 27 May 2013
© NXP B.V. 2013. All rights reserved.
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