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MAX2079CXE Ver la hoja de datos (PDF) - Maxim Integrated

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MAX2079CXE Datasheet PDF : 49 Pages
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MAX2079
Low-Power, High-Performance, Fully Integrated
Octal Ultrasound Receiver (Octal LNA, VGA,
AAF, ADC, and CWD Beamformer)
AC ELECTRICAL CHARACTERISTICS—VGA MODE (CWD Beamformer Off) (continued)
(VREF = 2.5V, VCC3 = 3.13V to 3.47V, VCC5 = 4.5V to 5.25V, VAVDD = VOVDD = 1.7V to 1.9V, TA = 0NC to +70NC, VGND = 0V, SHDN = 0,
CWD = 0, LOON = 0, fRF = 5MHz, 50mVP-P, ADC fCLK = 50Msps, digital HPF set to 60/64, two poles, 15/16 digital gain, VGC+ -
VGC- = -3V (minimum gain), high LNA gain. Typical values are at VREF = 2.5V, VCC3 = 3.3V, VCC5 = 4.75V, VAVDD = VOVDD = 1.8V,
VGC+ - VGC- = 0V, TA = +25NC, unless otherwise noted.) (Note 3)
PARAMETER
CONDITIONS
MIN
8-Channel Correlated Noise
Power
No input signal, ratio of 8-channel noise power to
single-channel noise power
5MHz signal applied to all 8 channels, VGC+ - VGC- = 0V,
fRF = 5MHz at -3dBFS, ratio of 8-channel noise power to
single-channel noise power
LNA Gain (Low LNA Gain)
LNA Gain (High LNA Gain)
Maximum Gain (High LNA Gain) VGC+ - VGC- = +3V (max gain), LNA input to ADC Input
Minimum Gain (High LNA Gain) VGC+ - VGC- = -3V (min gain), LNA input to ADC Input
Maximum Gain (Low LNA Gain) VGC+ - VGC- = +3V (max gain), LNA input to ADC Input
Minimum Gain (Low LNA Gain) VGC+ - VGC- = = -3V (min gain), LNA input to ADC input
Gain Range
9MHz setting
10MHz setting
AA Filter 3dB Corner Frequency
15MHz setting
18MHz setting
AA Filter 3dB Corner Frequency
Accuracy
Digital Highpass Filter 3dB
Corner Frequency
Clamp Level
2 poles, coefficients R1 = R2 = 63/64, fCLK = 50Msps
2 poles, coefficients R1 = R2 = 54/64, fCLK = 50Msps
Clamp on (VP-P on AAF Output/ADC Input, digital HPF
bypassed)
Device-to-Device Gain Matching TA = +25NC, VGC+ - VGC- = -3V to +3V (Note 6)
-1.6
Input Gain Compression
LNA = high gain, VGC+ - VGC- = -3V (VGA = min gain),
gain ratio with 330mVP-P/50mVP-P input tones
LNA = low gain, VGC+ - VGC- = -3V (VGA = min gain),
gain ratio with 600mVP-P/50mVP-P input tones
VGA Gain Response Time
Gain step up (VIN = 5mVP-P, VGC+ - VGC- changed from
-3V to +3V, settling time is measured within 1dB final value)
Gain step down (VIN = 5mVP-P, VGC+ - VGC- changed from
-3V to +3V, settling time is measured within 1dB final value)
VGA Output Offset Under
Pulsed Overload
Over drive is Q10mA in clamping diodes, VGC+ - VGC- =
1.0V (gain = 30dB), 16 pulses at 5MHz, repetition rate
20kHz; offset is measured at output when RF duty cycle is off
Signal-to-Noise Over ADC
Nyquist Band (25MHz)
VOUT_ = -1dBFS, VIN = 200mVP-P, fRF = 5MHz at -1dBFS,
anti-alias filter = 9MHz, 50Msps sample rate
TYP
9.0
8.5
12.5
18.5
44.7
5.9
40.4
1.4
38.8
9
10
15
18
Q10
0.185
1.736
92
Q0.5
0.7
0.9
0.8
1.8
< 3.3
67
MAX
+1.6
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
MHz
%
MHz
%FS
dB
dB
Fs
%FS
dBFS
Maxim Integrated
  4

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