AD7091R-4BRUZ Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Lista de partido
AD7091R-4BRUZ Datasheet PDF : 42 Pages
| |||
Data Sheet
AD7091R-2/AD7091R-4/AD7091R-8
CS 1
RESET 2
20 VDRIVE
19 CONVST
VDD 3
18 SCLK
REGCAP 4
17 SDO
REFIN/REFOUT 5 AD7091R-4 16 SDI
TOP VIEW
GND 6 (Not to Scale) 15 GND
MUXOUT 7
14 ADCIN
VIN0 8
13 VIN1
VIN2 9
12 VIN3
ALERT/BUSY/GPO0 10
11 GPO1
Figure 7. 4-Channel, 20-Lead TSSOP Pin Configuration
VDD 1
REGCAP 2
REFIN/REFOUT 3
GND 4
MUXOUT 5
AD7091R-4
TOP VIEW
(Not to Scale)
15 SDO
14 SDI
13 GND
12 ADCIN
11 VIN1
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO GND.
Figure 8. 4-Channel, 20-Lead LFCSP Pin Configuration
Table 6. 4-Channel, 20-Lead LFCSP and 20-Lead TSSOP Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic
Description
1
19
CS
Chip Select Input. When CS is held low, the serial bus enables, and CS frames the output data on
the SPI.
2
20
RESET
Reset. Logic input.
3
1
VDD
4
2
REGCAP
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. Decouple this supply pin to GND.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this output pin
separately to GND using a 1.0 μF capacitor.
5
3
REFIN/REFOUT
6, 15
4, 13 GND
Voltage Reference Output, 2.5 V. Decouple this pin to GND. Typical recommended decoupling
capacitor value is 2.2 μF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with the voltage applied to this pin. The reference voltage range for an
externally applied reference is 1.0 V to VDD.
Chip Ground Pins. These pins are the ground reference point for all circuitry on the AD7091R-4.
7
5
MUXOUT
8
6
VIN0
Multiplexer Output. The output of the multiplexer appears at this pin. If no external filtering or
buffering is required, tie this pin directly to the ADCIN pin; otherwise, tie the output of the
conditioning network to the ADCIN pin.
Analog Input 0. Single-ended analog input. The analog input range is 0 V to VREF.
9
7
VIN2
Analog Input 2. Single-ended analog input. The analog input range is 0 V to VREF.
10
8
ALERT/BUSY/GPO0 Alert Output Pin (ALERT). This is a multifunction pin determined by the configuration register.
When functioning as ALERT, this pin is a logic output indicating that a conversion result has
fallen outside the limit of the register settings.
When the ALERT/BUSY/GPO0 pin is configured as a BUSY output, use this pin to indicate when a
conversion is taking place.
The pin can also function as a general-purpose digital output.
11
9
GPO1
12
10
VIN3
13
11
VIN1
14
12
ADCIN
16
14
SDI
General-Purpose Digital Output.
Analog Input 3. Single-ended analog input. The analog input range is 0 V to VREF.
Analog Input 1. Single-ended analog input. The analog input range is 0 V to VREF.
ADC Input. This pin allows access to the on-chip track-and-hold. If no external filtering or
buffering is required, tie this pin directly to the MUXOUT pin; otherwise, tie the input of the
conditioning network to the MUXOUT pin.
Serial Data Input Bus. This input provides data written to the on-chip control registers. Data
clocks into the registers on the falling edge of the SCLK input. Provide data MSB first.
17
15
SDO
Serial Data Output Bus. The conversion output data is supplied to this pin as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input, and 13 SCLKs are
required to access the data. The data is provided MSB first.
Rev. C | Page 9 of 42
Share Link: 