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MAX2165ETI

Single-Conversion DVB-H Tuner

Maxim Integrated 

Single-Conversion DVB-H Tuner

Table 1. Register Configuration*

REGISTER SETTINGS MSB

REGISTER REGISTER

NAME

ADDRESS OPERATION DEFAULT

DEFINED

(POR)

D7

D6

D5

DATA BYTE

D4

D3

N-Divider Integer 0x00

—

H17

N7

N6

N5

N4

N3

U

U

U

U

U

N-Divider Frac2

0x01

—

H18

X

X

X

FRAC

F19

0

0

0

U

U

N-Divider Frac1

0x02

—

H00

F15

U

F14

U

F13

U

F12

U

F11

U

N-Divider Frac0

0x03

—

H00

F7

F6

F5

F4

F3

U

U

U

U

U

Tracking Filter

0x04

—

H72

TF_NTCH3 TF_NTCH2 TF_NTCH1 TF_NTCH0

U

U

U

U

TF_BAL3

U

LNA

0x05

—

H01

X

0

X

0

X

0

X

0

X

0

PLL

Configuration

0x06

—

H0A

RDIV

U

ICP

U

CPS

ADLY0

ADLY0

U

U

U

Test

0x07

—

H08

CP_TST2

0

CP_TST1

0

CP_TST0

0

X

0

X

1

Shutdown

0x08

—

H00

X

SHDN_REF

X

SHDN_SYN SHDN_RF

0

U

0

U

U

VCO Control

0x09

—

H50

VCO1

U

VCO0

U

BS2

U

BS1

U

BS0

U

Baseband

Control

0x0A

—

HF3

BB_BW3

U

BB_BW2

U

BB_BW1

U

BB_BW0

U

BB_BIA0

0

DC Offset Control 0x0B

H79

H71

X

DC_DAC8 DC_MO1

DC_MO0

DC_SP1

0

1

1

1

DC Offset DAC

0x0C

H00

H00

DC_DAC7 DC_DAC6 DC_DAC5 DC_DAC4

DC_DAC3

0

0

0

0

0

ROM Table

0x0D

—

H00

X

FUSE_TH

X

Address

0

0

0

WR

TFA3

0

U

Reserved

0x0E

H00

H00

X

0

X

0

X

0

X

0

X

0

ROM Table Data

Readback

0x10

N/A

N/A

TRF7

TRF6

TRF5

TRF4

TRF3

Chip Status

0x11

N/A

N/A

POR

VASA

VASE

LD

DC_LO

Readback

Autotuner

Readback

0x12

N/A

N/A

VCO1

VCO0

BS2

BS1

BS0

*See the Register Descriptions section for more information on recommended settings.

LSB

D2

N2

U

F18

U

F10

U

F2

U

TF_BAL2

U

X

0

LFDIV2

U

LD_MUX2

U

SHDN_BB

U

VAS

1

PD_TH2

U

DC_SP0

0

DC_DAC2

0

TFA2

U

X

0

TRF2

D1

N1

U

F17

U

F9

U

F1

U

TF_BAL1

U

X

0

LFDIV1

U

LD_MUX1

U

SHDN_PD

U

ADL

0

PD_TH1

U

DC_TH1

0

DC_DAC1

0

TFA1

U

X

0

D0

N0

U

F16

U

F8

U

F0

U

TF_BAL0

U

LNASW

U

LFDIV0

U

LD_MUX0

U

SHDN_BG

U

ADE

0

PD_TH0

U

DC_TH0

0

DC_DAC0

0

TFA0

U

X

0

TRF1

TRF0

DC_HI

X

PD_OVLD

ADC2

ADC1

ADC0

Table 2. N-Divider Integer Register (Address: 0x00)

BIT NAME

N[7:0]

BIT LOCATION

(0 = LSB)

7–0

FUNCTION

Programs the integer value of the PLL N-divider ratio. Default integer divide value is 23.

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