ST16C552CJ68TR-F Ver la hoja de datos (PDF) - Unspecified

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ST16C552CJ68TR-F

DUAL UART WITH 16-BYTE FIFO AND PARALLEL PRINTER PORT

Unspecified 

ST16C552/552A

Table 4, INTERNAL REGISTER DECODE

A2 A1 A0

READ MODE

WRITE MODE

General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1*

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

Receive Holding Register

Interrupt Status Register

Line Status Register

Modem Status Register

Scratchpad Register

Transmit Holding Register

Interrupt Enable Register

FIFO Control Register

Line Control Register

Modem Control Register

Scratchpad Register

Baud Rate Register Set (DLL/DLM): Note *2

0

0

0

0

0

1

LSB of Divisor Latch

MSB of Divisor Latch

LSB of Divisor Latch

MSB of Divisor Latch

Printer Port Set (PR/SR/IOSEL/COM/CON): Note *3

X

0

0

X

0

1

X

1

0

PORT REGISTER

STATUS REGISTER

COMMAND REGISTER

PORT REGISTER

I/O SELECT REGISTER

CONTROL REGISTER

Note 1* The General Register set is accessible only when CS A or CS B is a logic 0.

Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1.

Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the

interface signal BIDEN and Printer Control Register bit-5 or IOSEL register.

Rev. 3.40

10

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