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TDA8706A Datasheet PDF : 17 Pages
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Philips Semiconductors
6-bit analog-to-digital converter
with multiplexer and clamp
Product specification
TDA8706A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
tr
clock rise time
tf
clock fall time
10% to 90%; fclk ≤ 40 MHz; −
−
7
ns
LOW = 0.8 V,
HIGH = 2.0 V
90% to 10%; fclk ≤ 40 MHz; −
−
7
ns
LOW = 0.8 V,
HIGH = 2.0 V
Analog signal processing
LINEARITY
INL
DNL
integral non-linearity
differential non-linearity
fclk = 40 MHz; ramp input −
fclk = 40 MHz; ramp input −
EFFECTIVE BITS; note 2
EB
effective bits
fclk = 40 MHz;
5.5
fi = 4.43 MHz
Timing (fclk = 40 MHz; CL = 10 pF); see Fig.3
±0.20
±0.5
LSB
±0.10
±0.35
LSB
5.8
−
bits
OUTPUT DATA; note 3
tds
sampling delay time
th
output hold time
td
output delay time
SELECT INPUT SIGNALS SR, SG, SB AND CLP
−
−
7
ns
6.5
9.0
−
ns
−
12
19
ns
tsu
set-up time SR, SG and with no overlap; see Fig.3 10
−
−
ns
SB
with overlap; see Fig.4
−
−
−
ns
tr
rise time SR, SG and SB 10% to 90%
4
6
−
ns
tf
fall time SR, SG and SB 90% to 10%
tover
RED, GREEN and BLUE see Fig.4
(active) overlap time with
respect to select signals
SR, SG and SB
4
6
−
ns
0
−
−
ns
tCLPP
clamp pulse time
CCLP = 10 nF
−
3
−
µs
tMH
multiplexer hold time SR,
SG and SB
9
−
−
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns. A sine wave with specified amplitude is also allowed.
2. Effective bits are derived from a Fast Fourier Transform (FFT) processing taking 2K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
3. Output data acquisition: the output data is available after the maximum delay time td.
2003 Jul 21
7
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