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ITG3200

The ITG-3200 triple-axis MEMS gyroscope

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ITG-3200 Product Specification

Document Number: PS-ITG-3200A-00-01.4

Revision: 1.4

Release Date: 03/30/2010

6 Digital Interface

6.1 I2C Serial Interface

The internal registers and memory of the ITG-3200 can be accessed using I2C at up to 400kHz.

Serial Interface

Pin Number

8

9

23

24

Pin Name

VLOGIC

AD0

SCL

SDA

Pin Description

Digital IO supply voltage. VLOGIC must be ≤ VDD at all times.

I2C Slave Address LSB

I2C serial clock

I2C serial data

6.1.1 I2C Interface

I2C is a two wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are

open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or a

slave. The master device puts the slave address on the bus, and the slave device with the matching address

acknowledges the master.

The ITG-3200 always operates as a slave device when communicating to the system processor, which thus acts as the

master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400kHz.

The slave address of the ITG-3200 devices is b110100X which is 7 bits long. The LSB bit of the 7 bit address is

determined by the logic level on pin 9. This allows two ITG-3200 devices to be connected to the same I2C bus. When

used in this configuration, the address of the one of the devices should be b1101000 (pin 9 is logic low) and the address

of the other should be b1101001 (pin 9 is logic high). The I2C address is stored in register 0 (WHO_AM_I register).

I2C Communications Protocol

START (S) and STOP (P) Conditions

Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a

HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy

until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line

while SCL is HIGH (see figure below).

Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.

SDA

SCL

S

START condition

START and STOP Conditions

P

STOP condition

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