HM-6518 Ver la hoja de datos (PDF) - Intersil
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HM-6518 Datasheet PDF : 7 Pages
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HM-6518
AC Electrical Specifications VCC = 5V ± 10%; TA = -40oC to +85oC (HM-6518B-9, HM-6518-9)
LIMITS
PARAMETER
SYMBOL
HM-6518B-9
MIN MAX
HM-6518-9
MIN MAX
UNITS
TEST
CONDITIONS
Chip Enable Access Time
(1) TELQV
-
180
-
250
ns
(Notes 1, 3)
Address Access Time
(2) TAVQV
-
180
-
250
ns
(Notes 1, 3, 4)
Chip Select Output Enable Time
(3) TSLQX
5
120
5
160
ns
(Notes 2, 3)
Write Enable Output Disable Time
(4) TWLQZ
-
120
-
160
ns
(Notes 2, 3)
Chip Select Output Disable Time
(5) TSHQZ
-
120
-
160
ns
(Notes 2, 3)
Chip Enable Pulse Negative Width
(6) TELEH
180
-
250
-
ns
(Notes 1, 3)
Chip Enable Pulse Positive Width
(7) TEHEL
100
-
100
-
ns
(Notes 1, 3)
Address Setup Time
(8) TAVEL
0
-
0
-
ns
(Notes 1, 3)
Address Hold Time
(9) TELAX
40
-
50
-
ns
(Notes 1, 3)
Data Setup Time
(10) TDVWH
80
-
110
-
ns
(Notes 1, 3)
Data Hold Time
(11) TWHDX
0
-
0
-
ns
(Notes 1, 3)
Chip Select Write Pulse Setup Time
(12) TWLSH
100
-
130
-
ns
(Notes 1, 3)
Chip Enable Write Pulse Setup Time
(13) TWLEH
100
-
130
-
ns
(Notes 1, 3)
Chip Select Write Pulse Hold Time
(14) TSLWH
100
-
130
-
ns
(Notes 1, 3)
Chip Enable Write Pulse Hold Time
(15) TELWH
100
-
130
-
ns
(Notes 1, 3)
Write Enable Pulse Width
(16) TWLWH
100
-
130
-
ns
(Notes 1, 3)
Read or Write Cycle Time
(17) TELEL
280
-
350
-
ns
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0.8V to VCC - 2.0V; input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. VCC = 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
6-4
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