NTE1639 Ver la hoja de datos (PDF) - NTE Electronics

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NTE1639

Integrated Circuit CMOS Clock Generator/Driver for BBDs

NTE Electronics 

Pin Descriptions:

Pin No. Symbol

Pin Name

Description

1

GND

Ground

Connected to GND of the circuit.

2

CP1

Clock Output 1 This pin outputs a clock signal that is the reverse

phase of CP2 with a Duty Cycle of 1/2 the frequency

of oscillation.

3

VDD

VDD apply

–15V is applied

4

CP2

Clock Output 2 This pin outputs a clock signal that is a the reverse

phase of CP1

5

OX3 OSC connections to R, C are connected for the In case of separate excita-

6

OX2

C1, R2, and R1

separately

internal clock.

tion, OX3 and OX2 are

opened and OX1 is set to

7

OX1

OSC input.

8 VGG OUT VGG Voltage Output –14V is output. (VDD = –15V) VGG OUT = 14/15VDD.

The Maximum Clock Frequency:

The upper limit value of the clock frequency is determined by the load capacitance and power con-

sumption. The maximum power dissipation for the NTE1639 is PD = 200mW. If the clock frequency

of the load capacitance is increased, the power consumption will be increased. Accordingly, in order

to utilize this device with a dissipation less than the permissible value, it is necessary to select ade-

quate values for the clock frequency and load capacitance. By connecting a resistance to the clock

output pin, it is possible to increase the value of the maximum clock frequency without increasing dis-

sipation. Because the dissipation on the LSI side is lessened, part of the power consumption required

for driving the load capacitance is consumed by the series resistance.

Pin Connection Diagram

GND 1

CP 1 2

VDD 3

CP 2 4

8 VGG (Out)

7 OX 1

6 OX 2

5 OX 3

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