CY62128EV30LL-55ZXET(2012) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY62128EV30LL-55ZXET Datasheet PDF : 18 Pages
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CY62128EV30 MoBL® Automotive
Switching Waveforms (continued)
Figure 9. Write Cycle No. 2 (CE1 or CE2 Controlled) [27, 28, 29, 30]
tWC
ADDRESS
CE
WE
DATA I/O
tSCE
tSA
tAW
tHA
tPWE
tSD
tHD
DATAINVALID
ADDRESS
CE
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 30]
tWC
tSCE
tSA
WE
DATA I/O
NOTE 31
tHZWE
tAW
tHA
tPWE
tSD
DATAINVALID
tHD
tLZWE
Notes
27. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH
28. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
29. Data I/O is high impedance if OE = VIH.
30. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
31. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-65528 Rev. *B
Page 10 of 18
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