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CYIL2SM1300-EVAL

LUPA 1300-2: High Speed CMOS Image Sensor

ON Semiconductor 

CYIL2SM1300AA

Table 13. Internal Registers (continued)

Block

Sequencer

Register Name Address [6..0]

seqmode1

56

seqmode2

57

seqmode3

58

Field

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[4:0]

[6:5]

[0]

[1]

[2]

[5:3]

[6]

[7]

Reset Value

Description

0

Enables image capture

1

‘1’: Master mode, integration timing is generated

on-chip

‘0’: Slave mode, integration timing is controlled

off-chip through INT_TIME1, INT_TIME2 and

INT_TIME3 pins

0

‘0’: Pipelined mode

‘1’: Triggered mode

0

Enables(‘1’)/disables(‘0’) subsampling

0

‘1’: Color subsampling scheme: 1:1:0:0:1:1:0:0

‘0’: B&W subsampling scheme: 1:0:1:0:1

0

Enable dual slope

0

Enable triple slope

0

Enables continued row select (that is, assert row

select during pixel read out)

‘10000’

Must be overwritten with‘10001’ to this register after

startup, before readout.

‘00’

Number of active windows:

“00”: 1 window

“01”: 2 windows

“10”: 3 windows

“11”: 4 windows

‘1’

Enables the generation of the CRC10 on the data

and sync channels

‘0’

Not applicable

‘0’

Enable column fpn calibration

“001”

Number of frames in nondestructive read out:

“000”: invalid

“001”: one reset, one sample (default mode)

“010”: one reset, two samples

…

0

Controls the granularity of the timer settings (only for

those that have ‘granularity selectable’ in the

description):

‘0’: Expressed in number of lines

‘1’: Expressed in clock cycles (multiplied by

2**seqmode4[3:0])

0

Allows delaying the syncing of events that happen

outside of ROT to the next ROT. This avoids image

artefacts.

Document Number: 001-24599 Rev. *C

Page 13 of 41

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