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MEC1310

Keyboard and Embedded Controller for Notebook PC

Microchip Technology 

MEC1310

• 56 General Purpose I/O Pins

- Maskable Hardware Wake-Event Capable

- Programmable Open-Drain/Push-Pull Out-

puts

• 7 General-Purpose Outputs

• Four Programmable Pulse-Width Modulator Out-

puts

- Independent Clock Rates

- 6-Bit Duty Cycle Granularity

- Operational in both Full on and Standby

modes

• Dual Fan Tachometer Inputs

• RPM-Based Fan Speed Control Algorithm

- Utilizes one TACH input and one PWM output

- 3% accurate from 500 RPM to 16k RPM

- Automatic Tachometer feedback

- Aging Fan or Invalid Drive Detection

- Spin Up Routine

- Ramp Rate Control

– RPM-based Fan Speed Control Algorithm

• Debug Port (UART)

- High-Speed 16550A-Compatible UART with

16-Byte Send/Receive FIFOs

- Programmable Baud Rate Generator

- Relocatable to 480 Different Base I/O

Addresses

- 15 IRQ Options

• BC-Link Interconnection Bus

- Combined High Speed/Low Speed Bus Mas-

ter Controller

• General Purpose Analog to Digital Converter (GP-

ADC)

- 10-bit conversion precision

- 10-bit conversion per channel is completed in

10.91us

- 5 ADC channels

– 10-bit Conversion with 25.78 mV resolution

– 0 to 3.3 VDC Conversion Range

- Channel 0 has a 5 volt tolerant input

- Optional continuous sampling at a program-

mable rate

- Selectable VREF source on a per Channel

Basis

– VREF pin or AVCC

• 128-Pin VTQFP RoHS Compliant Package

Description

The MEC1310 is a 128-pin 3.3V LPC-based ACPI 2.0

and PC99/PC2001 compliant Notebook I/O Controller.

See FIGURE 1: MEC1310 Block Diagram on page 4.

The MEC1310 incorporates a high-performance 8051-

based keyboard and system controller with internal

embedded 64K SRAM; a 1K byte Boot ROM, and 64-

bytes battery backed registers. The embedded 64K

SRAM is loaded via HOST/8051 SPI Memory Inter-

face. The HOST/8051 SPI Memory Interface can be

configured in Switched SPI Flash Configuration or Par-

allel Shared SPI Flash Configuration.

The MEC1310 has four PS/2 ports; an 16C550A-com-

patible 2 pin UART for Debug Port; three 8584-style

I2C/SMBus controllers with two selectable ports per

controller; a Serial IRQ peripheral agent interface;

three ACPI Embedded Controller Interface; General

Purpose I/O pins and seven General Purpose Outputs;

four independently programmable pulse width modula-

tors; dual fan control through the implementation of two

fan tachometer input pins, RPM-PWM block with one

tachometer input and one PWM output; hardware mon-

itoring of a PWM input and maskable hardware wake-

up events; one BC-Link Combined High Speed/Low

Speed Bus Master Controller; 5 channel Analog to Dig-

ital Converter.

The MEC1310 has two separate power planes to pro-

vide “instant on” and system power management func-

tions. Additionally, the MEC1310 incorporates

sophisticated power control circuitry (PCC). The PCC

supports multiple low power down modes. Wake-up

events and ACPI-related functions are supported

through the SCI Interface.

The MEC1310 supports the ISA Plug-and-Play Stan-

dard (Version 1.0a) and provides all the functionality for

current Windows O/S’s. The I/O Address and Hard-

ware IRQ of each logical device in the MEC1310 may

be reprogrammed through the internal configuration

registers. There are 480 I/O address location options

and 15 IRQs for each logical device.

DS00001768A-page 2

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 2014 Microchip Technology Inc.

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