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PSB7280

Joint Audio Decoder-Encoder

Infineon Technologies 

PSB 7280

2

General Architecture and Functions

2.1

Architecture

Figure 6 shows a sketch of the PSB 7280 architecture with its most important functional

modules.

SIO A D(0 :7) A(0 :3) RD# WR# CS# A L E INTR# IN T#

Re se t

EA#

Parallel Host Interface

Mon, C/I

Con tr ol

A u di o

Rec 1

SC LK

SR

Serial

ST

A ud i o

I/F

R FS

TFS

Trm 1

Rec 2

Trm 2

HDLC 1

DD

IOM/

DU

PCM

HDLC 2

D CL

2M52Ma65ial6bbiylobbtxyeotxe

F SC

Confi g/ Control

Regis ters

32 KW program

ROM

DSP

Core

Tim ers

8 KW dat a 2 KW dat a

X-RO M

X- RA M

1 KW data 1 KW data

X -RAM

Y-RA M

External Memor y Interface

BRG

clock

gen /

PLL

GPIO

I/F

C M1

C L KO

XTA L1

XTA L2

G P(0:3 )

CA(0 :15 ) C D(0 :15) CRD# CWR# CPS# CDS#

Figure 6

The audio processing of the PSB 7280 is based on a 16-bit fixed point DSP core, SPCF

(Signal Processor Core Fast).

The Clock Generator is responsible for generating the internal clocks for the SPCF. A

Baud Rate Generator provides an output clock of programmable rate.

The Parallel Host Interface is used to control the circuit through an associated host via

interrupt handshake procedures. Alternatively, the circuit can be controlled via the serial

audio interface, thus enabling standalone applications to be implemented.

Communication between the host, if used, and the DSP is interrupt supported, via a full-

duplex 256-byte on-chip Communication Memory Mailbox.

Semiconductor Group

21

Data Sheet 1998-07-01

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