74HC160 Ver la hoja de datos (PDF) - NXP Semiconductors.
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74HC160 Datasheet PDF : 19 Pages
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Nexperia
74HC160
Presettable synchronous BCD decade counter; asynchronous reset
5. Pinning information
5.1 Pinning
+&
05
&3
'
'
'
'
&(3
*1'
9&&
7&
4
4
4
4
&(7
3(
DDD
Fig 5. Pin configuration SO16
5.2 Pin description
Table 2. Pin description
Symbol
MR
CP
D0, D1, D2, D3
CEP
GND
PE
CET
Q0, Q1, Q2, Q3
TC
VCC
Pin
1
2
3, 4, 5, 6
7
8
9
10
14, 13, 12, 11
15
16
+&
05
&3
'
'
'
'
&(3
*1'
9&&
7&
4
4
4
4
&(7
3(
DDD
Fig 6. Pin configuration SSOP16
Description
asynchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge triggered)
data input
count enable input
ground (0 V)
parallel enable input (active LOW)
count enable carry input
flip-flop output
terminal count output
supply voltage
74HC160
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 September 2016
© Nexperia B.V. 2017. All rights reserved
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