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74LVC245A-Q100

Octal bus transceiver; 3-state

NXP Semiconductors. 

Nexperia

74LVC245A-Q100; 74LVCH245A-Q100

Octal bus transceiver; 3-state

5. Pinning information

5.1. Pinning

74LVC245A-Q100

74LVCH245A-Q100

DIR 1

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9

GND 10

20 VCC

19 OE

18 B0

17 B1

16 B2

15 B3

14 B4

13 B5

12 B6

11 B7

aaa-003142

Fig. 3. Pin configuration SOT163-1 (SO20)

and SOT360-1 (TSSOP20)

74LVC245A-Q100

74LVCH245A-Q100

terminal 1

index area

A0 2

A1 3

A2 4

A3 5

A4 6

A5 7

A6 8

A7 9

GND(1)

19 OE

18 B0

17 B1

16 B2

15 B3

14 B4

13 B5

12 B6

aaa-003143

Fig. 4.

Transparent top view

(1) This is not a supply pin. The substrate is

attached to this pad using conductive die attach

material. There is no electrical or mechanical

requirement to solder this pad. However, if it is

soldered, the solder land should remain floating or

be connected to GND.

Pin configuration SOT764-1 (DHVQFN20)

5.2. Pin description

Table 2. Pin description

Symbol

DIR

A0, A1, A2, A3, A4, A5, A6, A7

GND

B0, B1, B2, B3, B4, B5, B6, B7

OE

VCC

Pin

1

2, 3, 4, 5, 6, 7, 8, 9

10

18, 17, 16, 15, 14, 13, 12, 11

19

20

Description

direction control

data input/output

ground (0 V)

data input/output

output enable input (active LOW)

supply voltage

6. Functional description

Table 3. Function selection

H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance OFF-state.

Inputs

Inputs/outputs

OE

DIR

An

Bn

L

L

An = Bn

inputs

L

H

inputs

Bn = An

H

X

Z

Z

74LVC_LVCH245A_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 11 September 2018

© Nexperia B.V. 2018. All rights reserved

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