AD7452_15 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Lista de partido
AD7452_15 Datasheet PDF : 24 Pages
| |||
Data Sheet
CIRCUIT INFORMATION
The AD7452 is a 12-bit, low power, single-supply, successive
approximation analog-to-digital converter (ADC). It can
operate with a 5 V or 3 V power supply, and is capable of
throughput rates up to 555 kSPS when supplied with a 10 MHz
SCLK. It requires an external reference to be applied to the VREF
pin, with the value of the reference chosen depending on the
power supply and what suits the application.
When operated with a 5 V supply, the maximum reference that
can be applied is 3.5 V. When operated with a 3 V supply, the
maximum reference that can be applied is 2.2 V (see the
Reference section).
The AD7452 has an on-chip differential track-and-hold
amplifier, a successive approximation (SAR) ADC, and a serial
interface, housed in an 8-lead SOT-23 package. The serial clock
input accesses data from the part and provides the clock source
for the successive approximation ADC. The AD7452 features a
power-down option for reduced power consumption between
conversions. The power-down feature is implemented across
the standard serial interface as described in the Modes of
Operation section.
CONVERTER OPERATION
The AD7452 is a successive approximation ADC based around
two capacitive DACs. Figure 18 and Figure 19 show simplified
schematics of the ADC in the acquisition and conversion phase,
respectively. The ADC is comprised of control logic, an SAR,
and two capacitive DACs. In Figure 18 (acquisition phase), SW3
is closed and SW1 and SW2 are in Position A, the comparator is
held in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
CAPACITIVE
DAC
VIN+
VIN–
B
CS
A
SW1
A
SW2
B
VREF
CS
SW3
CONTROL
LOGIC
COMPARATOR
CAPACITIVE
DAC
Figure 18. ADC Acquisition Phase
AD7452
When the ADC starts a conversion (Figure 19), SW3 opens and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC’s output code. The output impedances of the
sources driving the VIN+ and the VIN– pins must be matched;
otherwise, the two inputs will have different settling times,
resulting in errors.
CAPACITIVE
DAC
VIN+
VIN–
B
CS
A
SW1
A
SW2
B
CS
VREF
SW3
CONTROL
LOGIC
COMPARATOR
CAPACITIVE
DAC
Figure 19. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7452 is twos complement. The
designed code transitions occur at successive LSB values
(that is, 1 LSB, 2 LSBs, and so on). The LSB size is 2 ×
VREF/4096. The ideal transfer characteristic of the AD7452 is
shown in Figure 20.
011...111
011...110
1LSB = 2 × VREF/4096
000...001
000...000
111...111
100...010
100...001
100...000
–VREF 1LSB
0 LSB
+ VREF – 1LSB
ANALOG INPUT
(VIN+ –VIN–)
Figure 20. Ideal Transfer Characteristic
Rev. C | Page 13 of 24
Share Link: 