AD7452 Ver la hoja de datos (PDF) - Analog Devices
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AD7452 Datasheet PDF : 24 Pages
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Data Sheet
AD7452
+2.5V
0V
–2.5V
R
R
VIN
R
R
0.1F
5V
2.5V
0V
VIN+
AD7452
VIN–
VREF
EXTERNAL
VREF (2.5V)
Figure 34. Applying a Bipolar Single-Ended Input to the AD7452
SERIAL INTERFACE
Figure 2 shows a detailed timing diagram for the serial interface
of the AD7452. The serial clock provides the conversion clock
and also controls the transfer of data from the device during
conversion. CS initiates the conversion process and frames the
data transfer. The falling edge of CS puts the track-and-hold
into hold mode and takes the bus out of three-state. The analog
input is sampled and the conversion is initiated at this point.
The conversion requires 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
goes back into track on the next SCLK rising edge, as shown at
Point B in Figure 2. On the 16th SCLK falling edge, the SDATA
line goes back into three-state. If the rising edge of CS occurs
before 16 SCLKs have elapsed, the conversion is terminated and
the SDATA line goes back into three-state.
The conversion result from the AD7452 is provided on the
SDATA output as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. The data stream of the
AD7452 consists of four leading zeros followed by 12 bits of
conversion data provided MSB first. The output coding is twos
complement.
Sixteen serial clock cycles are required to perform a conversion
and access data from the AD7452. CS going low provides the
first leading zero to be read in by the microcontroller or DSP.
The remaining data is then clocked out on the subsequent
SCLK falling edges beginning with the second leading zero.
Thus, the first falling clock edge on the serial clock provides the
second leading zero. The final bit in the data transfer is valid on
the 16th falling edge, having been clocked out on the previous
(15th) falling edge. Once the conversion is complete and the data
has been accessed after the 16 clock cycles, it is important to
ensure that before the next conversion is initiated, enough time
is left to meet the acquisition, and quiet time specifications (see
the Timing Example).
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge, that is, the first rising edge of
SCLK after the CS falling edge would have the leading zero
provided and the 15th SCLK edge would have DB0 provided.
Timing Example
Having fSCLK = 10 MHz and a throughput rate of 555 kSPS gives
a cycle time of
1/Throughput = 1/555,000 = 1.8 μs
A cycle consists of
t2 + 12.5(1/fSCLK) + tACQ = 1.8 μs
Therefore, if t2 = 10 ns
10 ns + 12.5(1/10 MHz) + tACQ = 1.8 μs
tACQ = 540 ns
This 540 ns satisfies the requirement of 290 ns for tACQ.
From Figure 35, tACQ comprises
2.5(1/fSCLK) + t8 + tQUIET
where t8 = 35 ns. This allows a value of 255 ns for tQUIET,
satisfying the minimum requirement of 60 ns.
CS
10ns
t2
t5
tCONVERT
SCLK
1
2
3
4
5
13
14
15
16
t6
t8
12.5(1/fSCLK)
1/THROUGHPUT
tACQUISITION
tQUIET
Figure 35. Serial Interface Timing Example
Rev. C | Page 19 of 24
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